CodeGen: Make all targets override pseudos with pointers#159881
Merged
Conversation
Contributor
Author
This stack of pull requests is managed by Graphite. Learn more about stacking. |
This was referenced Sep 19, 2025
arsenm
added
backend:AMDGPU
backend:SystemZ
llvm:codegen
llvm:globalisel
llvm:mc
Graphite App
Member
|
@llvm/pr-subscribers-backend-amdgpu Author: Matt Arsenault (arsenm) ChangesThis eliminates the need to have PointerLikeRegClass handling in Full diff: https://github.com/llvm/llvm-project/pull/159881.diff 26 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 86f95488e6bb7..d98c235dab15e 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -40,6 +40,8 @@ include "AArch64SchedPredExynos.td"
include "AArch64SchedPredNeoverse.td"
include "AArch64Combine.td"
+defm : RemapAllTargetPseudoPointerOperands<GPR64sp>;
+
def AArch64InstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/R600.td b/llvm/lib/Target/AMDGPU/R600.td
index 9148edb92b084..bdfaac9f42ea7 100644
--- a/llvm/lib/Target/AMDGPU/R600.td
+++ b/llvm/lib/Target/AMDGPU/R600.td
@@ -8,15 +8,6 @@
include "llvm/Target/Target.td"
-def R600InstrInfo : InstrInfo {
- let guessInstructionProperties = 1;
-}
-
-def R600 : Target {
- let InstructionSet = R600InstrInfo;
- let AllowRegisterRenaming = 1;
-}
-
let Namespace = "R600" in {
foreach Index = 0-15 in {
@@ -27,6 +18,18 @@ include "R600RegisterInfo.td"
}
+defm : RemapAllTargetPseudoPointerOperands<R600_Addr>;
+
+def R600InstrInfo : InstrInfo {
+ let guessInstructionProperties = 1;
+}
+
+def R600 : Target {
+ let InstructionSet = R600InstrInfo;
+ let AllowRegisterRenaming = 1;
+}
+
+
def NullALU : InstrItinClass;
def ALU_NULL : FuncUnit;
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 88a26832980d6..eecccd2e0e395 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -4745,3 +4745,14 @@ def V_ILLEGAL : Enc32, InstSI<(outs), (ins), "v_illegal"> {
let hasSideEffects = 1;
let SubtargetPredicate = isGFX10Plus;
}
+
+defvar VGPR32_Ptr_Opcodes = [LOAD_STACK_GUARD];
+defvar VGPR64_Ptr_Opcodes = !listremove(PseudosWithPtrOps, VGPR32_Ptr_Opcodes);
+
+foreach inst = VGPR32_Ptr_Opcodes in {
+ def : RemapPointerOperands<inst, VGPR_32>;
+}
+
+foreach inst = VGPR64_Ptr_Opcodes in {
+ def : RemapPointerOperands<inst, VReg_64_AlignTarget>;
+}
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index 570aae9b3c7a7..1f71d810983db 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -38,6 +38,14 @@ include "ARMSchedule.td"
//===----------------------------------------------------------------------===//
include "ARMInstrInfo.td"
+
+def Thumb1OnlyMode : HwMode<[IsThumb1Only]>;
+def arm_ptr_rc : RegClassByHwMode<
+ [DefaultMode, Thumb1OnlyMode],
+ [GPR, tGPR]>;
+
+defm : RemapAllTargetPseudoPointerOperands<arm_ptr_rc>;
+
def ARMInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AVR/AVR.td b/llvm/lib/Target/AVR/AVR.td
index 22ffc4a368ad6..f4ee11984cb73 100644
--- a/llvm/lib/Target/AVR/AVR.td
+++ b/llvm/lib/Target/AVR/AVR.td
@@ -32,6 +32,8 @@ include "AVRRegisterInfo.td"
include "AVRInstrInfo.td"
+defm : RemapAllTargetPseudoPointerOperands<PTRDISPREGS>;
+
def AVRInstrInfo : InstrInfo;
//===---------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/BPF/BPF.td b/llvm/lib/Target/BPF/BPF.td
index dff76ca07af51..399be731b44f6 100644
--- a/llvm/lib/Target/BPF/BPF.td
+++ b/llvm/lib/Target/BPF/BPF.td
@@ -13,6 +13,9 @@ include "BPFCallingConv.td"
include "BPFInstrInfo.td"
include "GISel/BPFRegisterBanks.td"
+
+defm : RemapAllTargetPseudoPointerOperands<GPR>;
+
def BPFInstrInfo : InstrInfo;
class Proc<string Name, list<SubtargetFeature> Features>
diff --git a/llvm/lib/Target/CSKY/CSKY.td b/llvm/lib/Target/CSKY/CSKY.td
index b5df93a9d464c..45ef9441b0a41 100644
--- a/llvm/lib/Target/CSKY/CSKY.td
+++ b/llvm/lib/Target/CSKY/CSKY.td
@@ -671,6 +671,8 @@ def : CK860V<"ck860fv", NoSchedModel,
// Define the CSKY target.
//===----------------------------------------------------------------------===//
+defm : RemapAllTargetPseudoPointerOperands<GPR>;
+
def CSKYInstrInfo : InstrInfo;
diff --git a/llvm/lib/Target/DirectX/DirectX.td b/llvm/lib/Target/DirectX/DirectX.td
index 4d1d45b84a683..1717d533d90fa 100644
--- a/llvm/lib/Target/DirectX/DirectX.td
+++ b/llvm/lib/Target/DirectX/DirectX.td
@@ -22,6 +22,8 @@ include "DXILStubs.td"
// DirectX Subtarget features.
//===----------------------------------------------------------------------===//
+defm : RemapAllTargetPseudoPointerOperands<DXILClass>;
+
def DirectXInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td
index 6d0529fb42779..332ce14504281 100644
--- a/llvm/lib/Target/Hexagon/Hexagon.td
+++ b/llvm/lib/Target/Hexagon/Hexagon.td
@@ -408,6 +408,8 @@ include "HexagonPatternsV65.td"
include "HexagonDepMappings.td"
include "HexagonIntrinsics.td"
+defm : RemapAllTargetPseudoPointerOperands<IntRegs>;
+
def HexagonInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Lanai/Lanai.td b/llvm/lib/Target/Lanai/Lanai.td
index c6d949f42047e..9a5422db5feeb 100644
--- a/llvm/lib/Target/Lanai/Lanai.td
+++ b/llvm/lib/Target/Lanai/Lanai.td
@@ -21,6 +21,8 @@ include "LanaiRegisterInfo.td"
include "LanaiCallingConv.td"
include "LanaiInstrInfo.td"
+defm : RemapAllTargetPseudoPointerOperands<GPR>;
+
def LanaiInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/LoongArch/LoongArch.td b/llvm/lib/Target/LoongArch/LoongArch.td
index 6497ff999f6fa..67f07f0a0370e 100644
--- a/llvm/lib/Target/LoongArch/LoongArch.td
+++ b/llvm/lib/Target/LoongArch/LoongArch.td
@@ -202,6 +202,8 @@ def : ProcessorModel<"la664", NoSchedModel, [Feature64Bit,
// Define the LoongArch target.
//===----------------------------------------------------------------------===//
+defm : RemapAllTargetPseudoPointerOperands<GPR>;
+
def LoongArchInstrInfo : InstrInfo {
let guessInstructionProperties = 0;
}
diff --git a/llvm/lib/Target/M68k/M68k.td b/llvm/lib/Target/M68k/M68k.td
index dab66d1022955..dfa44a423ae25 100644
--- a/llvm/lib/Target/M68k/M68k.td
+++ b/llvm/lib/Target/M68k/M68k.td
@@ -95,6 +95,8 @@ include "GISel/M68kRegisterBanks.td"
include "M68kInstrInfo.td"
+defm : RemapAllTargetPseudoPointerOperands<AR16>;
+
def M68kInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/MSP430/MSP430.td b/llvm/lib/Target/MSP430/MSP430.td
index 38aa30fcf4dd1..cb3949838f6f2 100644
--- a/llvm/lib/Target/MSP430/MSP430.td
+++ b/llvm/lib/Target/MSP430/MSP430.td
@@ -61,6 +61,8 @@ include "MSP430CallingConv.td"
include "MSP430InstrInfo.td"
+defm : RemapAllTargetPseudoPointerOperands<GR16>;
+
def MSP430InstrInfo : InstrInfo;
//===---------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index e18388c179108..6c8d177093c76 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -244,6 +244,8 @@ include "MipsScheduleI6400.td"
include "MipsScheduleP5600.td"
include "MipsScheduleGeneric.td"
+defm : RemapAllTargetPseudoPointerOperands<mips_ptr_rc>;
+
def MipsInstrInfo : InstrInfo {
}
diff --git a/llvm/lib/Target/NVPTX/NVPTX.td b/llvm/lib/Target/NVPTX/NVPTX.td
index 31c117a8c0fee..d41a43de95098 100644
--- a/llvm/lib/Target/NVPTX/NVPTX.td
+++ b/llvm/lib/Target/NVPTX/NVPTX.td
@@ -150,6 +150,16 @@ def : Proc<"sm_121", [SM121, PTX88]>;
def : Proc<"sm_121a", [SM121a, PTX88]>;
def : Proc<"sm_121f", [SM121f, PTX88]>;
+
+def Is64Bit : Predicate<"Subtarget->getTargetTriple().getArch() == Triple::nvptx64">;
+def NVPTX64 : HwMode<[Is64Bit]>;
+
+def nvptx_ptr_rc : RegClassByHwMode<
+ [DefaultMode, NVPTX64],
+ [B32, B64]>;
+
+defm : RemapAllTargetPseudoPointerOperands<nvptx_ptr_rc>;
+
def NVPTXInstrInfo : InstrInfo {
}
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index d491e88b66ad8..1b60d297588e5 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -793,6 +793,8 @@ def PPCAsmParserVariant : AsmParserVariant {
string BreakCharacters = ".";
}
+defm : RemapAllTargetPseudoPointerOperands<ppc_ptr_rc>;
+
def PPC : Target {
// Information about the instructions.
let InstructionSet = PPCInstrInfo;
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 6d8c1223adf78..4544de2ba3146 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -869,6 +869,10 @@ def PPCRegGxRCNoR0Operand : AsmOperandClass {
let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber";
}
+def ppc_ptr_rc : RegClassByHwMode<
+ [PPC32, PPC64],
+ [GPRC, G8RC]>;
+
def ptr_rc_nor0_by_hwmode : RegClassByHwMode<
[PPC32, PPC64],
[GPRC_NOR0, G8RC_NOX0]>;
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index b24d8637cb27f..f6f82fd9bb55f 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -96,6 +96,8 @@ def RISCVAsmWriter : AsmWriter {
int PassSubtarget = 1;
}
+defm : RemapAllTargetPseudoPointerOperands<GPR>;
+
def RISCV : Target {
let InstructionSet = RISCVInstrInfo;
let AssemblyParsers = [RISCVAsmParser];
diff --git a/llvm/lib/Target/SPIRV/SPIRV.td b/llvm/lib/Target/SPIRV/SPIRV.td
index 39a4131c7f1bd..cc9c7913af427 100644
--- a/llvm/lib/Target/SPIRV/SPIRV.td
+++ b/llvm/lib/Target/SPIRV/SPIRV.td
@@ -14,6 +14,8 @@ include "SPIRVInstrInfo.td"
include "SPIRVCombine.td"
include "SPIRVBuiltins.td"
+defm : RemapAllTargetPseudoPointerOperands<pID>;
+
def SPIRVInstrInfo : InstrInfo;
class Proc<string Name, list<SubtargetFeature> Features>
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 7137e5fbff4ff..70160f5b91dee 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -123,6 +123,8 @@ include "SparcCallingConv.td"
include "SparcSchedule.td"
include "SparcInstrInfo.td"
+defm : RemapAllTargetPseudoPointerOperands<sparc_ptr_rc>;
+
def SparcInstrInfo : InstrInfo;
def SparcAsmParser : AsmParser {
diff --git a/llvm/lib/Target/SystemZ/SystemZ.td b/llvm/lib/Target/SystemZ/SystemZ.td
index ec110645c62dd..070a4fbde1f06 100644
--- a/llvm/lib/Target/SystemZ/SystemZ.td
+++ b/llvm/lib/Target/SystemZ/SystemZ.td
@@ -57,6 +57,9 @@ include "SystemZInstrHFP.td"
include "SystemZInstrDFP.td"
include "SystemZInstrSystem.td"
+
+defm : RemapAllTargetPseudoPointerOperands<ADDR64Bit>;
+
def SystemZInstrInfo : InstrInfo { let guessInstructionProperties = 0; }
//===----------------------------------------------------------------------===//
@@ -98,7 +101,6 @@ def HLASMAsmWriter : AsmWriter {
//===----------------------------------------------------------------------===//
// Top-level target declaration
//===----------------------------------------------------------------------===//
-
def SystemZ : Target {
let InstructionSet = SystemZInstrInfo;
let AssemblyParsers = [SystemZAsmParser];
diff --git a/llvm/lib/Target/VE/VE.td b/llvm/lib/Target/VE/VE.td
index bb076bd9f6d41..aedce0f4ebc8f 100644
--- a/llvm/lib/Target/VE/VE.td
+++ b/llvm/lib/Target/VE/VE.td
@@ -30,6 +30,7 @@ include "VERegisterInfo.td"
include "VECallingConv.td"
include "VEInstrInfo.td"
+defm : RemapAllTargetPseudoPointerOperands<ve_ptr_rc>;
def VEInstrInfo : InstrInfo {}
def VEAsmParser : AsmParser {
diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.td b/llvm/lib/Target/WebAssembly/WebAssembly.td
index 089be5f1dc70e..67015ffcfc760 100644
--- a/llvm/lib/Target/WebAssembly/WebAssembly.td
+++ b/llvm/lib/Target/WebAssembly/WebAssembly.td
@@ -108,6 +108,14 @@ include "WebAssemblyRegisterInfo.td"
include "WebAssemblyInstrInfo.td"
+def WASM64 : HwMode<[HasAddr64]>;
+
+def wasm_ptr_rc : RegClassByHwMode<
+ [DefaultMode, WASM64],
+ [I32, I64]>;
+
+defm : RemapAllTargetPseudoPointerOperands<wasm_ptr_rc>;
+
def WebAssemblyInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 3af8b3e060a16..9fd8db2adc51e 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -798,6 +798,8 @@ include "X86Schedule.td"
include "X86InstrInfo.td"
include "X86SchedPredicates.td"
+defm : RemapAllTargetPseudoPointerOperands<x86_ptr_rc>;
+
def X86InstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/XCore/XCore.td b/llvm/lib/Target/XCore/XCore.td
index a97b3dd1d0a2b..fa8b9fe26bbe1 100644
--- a/llvm/lib/Target/XCore/XCore.td
+++ b/llvm/lib/Target/XCore/XCore.td
@@ -24,6 +24,8 @@ include "XCoreRegisterInfo.td"
include "XCoreInstrInfo.td"
include "XCoreCallingConv.td"
+defm : RemapAllTargetPseudoPointerOperands<GRRegs>;
+
def XCoreInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td
index 4ef885e19101e..eecf42f46f88b 100644
--- a/llvm/lib/Target/Xtensa/Xtensa.td
+++ b/llvm/lib/Target/Xtensa/Xtensa.td
@@ -44,6 +44,8 @@ include "XtensaCallingConv.td"
include "XtensaInstrInfo.td"
+defm : RemapAllTargetPseudoPointerOperands<AR>;
+
def XtensaInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
|
Collaborator
|
MSP430 changes are obviously ok :) |
arsenm
force-pushed
the
users/arsenm/tablegen/support-target-specialized-pseudos
branch
from
8f62ad4 to
74bae94
Compare
arsenm
force-pushed
the
users/arsenm/codegen/override-ptr-pseudos-all-targets
branch
from
9d77e6b to
64f0e18
Compare
arsenm
force-pushed
the
users/arsenm/codegen/override-ptr-pseudos-all-targets
branch
from
64f0e18 to
7bdd6d6
Compare
arsenm
force-pushed
the
users/arsenm/tablegen/support-target-specialized-pseudos
branch
from
74bae94 to
1746185
Compare
arsenm
force-pushed
the
users/arsenm/tablegen/support-target-specialized-pseudos
branch
from
1746185 to
fb3b386
Compare
arsenm
force-pushed
the
users/arsenm/codegen/override-ptr-pseudos-all-targets
branch
2 times, most recently
from
5189567 to
ccf4a7d
Compare
arsenm
force-pushed
the
users/arsenm/tablegen/support-target-specialized-pseudos
branch
from
fb3b386 to
310569d
Compare
Base automatically changed from
users/arsenm/tablegen/support-target-specialized-pseudos
to
main
November 19, 2025 01:22
Contributor
Author
|
ping |
🐧 Linux x64 Test Results
|
Contributor
|
I guess this needs rebasing |
arsenm
force-pushed
the
users/arsenm/codegen/override-ptr-pseudos-all-targets
branch
from
ccf4a7d to
29afbe2
Compare
This eliminates the need to have PointerLikeRegClass handling in codegen.
arsenm
force-pushed
the
users/arsenm/codegen/override-ptr-pseudos-all-targets
branch
from
29afbe2 to
c5d9a11
Compare
arsenm
deleted the
users/arsenm/codegen/override-ptr-pseudos-all-targets
branch
tanji-dg
pushed a commit
to tanji-dg/llvm-project
that referenced
this pull request
Nov 27, 2025
This eliminates the need to have PointerLikeRegClass handling in codegen.
GeneraluseAI
pushed a commit
to GeneraluseAI/llvm-project
that referenced
this pull request
Nov 27, 2025
This eliminates the need to have PointerLikeRegClass handling in codegen.
MaskRay
added a commit
that referenced
this pull request
Nov 29, 2025
This ports #159881 fix for other targets and fixes ``` error: missing target override for pseudoinstruction using PointerLikeRegClass ```
aahrun
pushed a commit
to aahrun/llvm-project
that referenced
this pull request
Dec 1, 2025
This ports llvm#159881 fix for other targets and fixes ``` error: missing target override for pseudoinstruction using PointerLikeRegClass ```
augusto2112
pushed a commit
to augusto2112/llvm-project
that referenced
this pull request
Dec 3, 2025
This eliminates the need to have PointerLikeRegClass handling in codegen.
augusto2112
pushed a commit
to augusto2112/llvm-project
that referenced
this pull request
Dec 3, 2025
This ports llvm#159881 fix for other targets and fixes ``` error: missing target override for pseudoinstruction using PointerLikeRegClass ```
kcloudy0717
pushed a commit
to kcloudy0717/llvm-project
that referenced
this pull request
Dec 4, 2025
This eliminates the need to have PointerLikeRegClass handling in codegen.
kcloudy0717
pushed a commit
to kcloudy0717/llvm-project
that referenced
this pull request
Dec 4, 2025
This ports llvm#159881 fix for other targets and fixes ``` error: missing target override for pseudoinstruction using PointerLikeRegClass ```
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
5 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
This eliminates the need to have PointerLikeRegClass handling in
codegen.